Join Us: Design of PCIe 5.0 Physical Layer
Join Us: Design of PCIe 5.0 Physical Layer
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The Analog Designer's Toolbox (ADT) IS HERE!
ASU Class 2021 Graduation Project
ASU Class 2021 Graduation Project
In Collaboration With Mentor, A Siemens Business
In Collaboration With Mentor, A Siemens Business
Background
Background
PCI Express (Peripheral Component Interconnect Express) is a computer expansion standard introduced by Intel in 2004. The latest generations introduced by the PCIe has various improvements over the older standards, including higher maximum bus throughput, lower I/O pin count and smaller physical footprint, better performance scaling for bus devices, and a more detailed error detection and reporting mechanism (Advanced Error Reporting, AER).
PCI Express (Peripheral Component Interconnect Express) is a computer expansion standard introduced by Intel in 2004. The latest generations introduced by the PCIe has various improvements over the older standards, including higher maximum bus throughput, lower I/O pin count and smaller physical footprint, better performance scaling for bus devices, and a more detailed error detection and reporting mechanism (Advanced Error Reporting, AER).
Who Can Apply?
Who Can Apply?
Ain Shams University (ASU), Faculty of Engineering, BSc Graduation Project Students Only (Class 2021)
Ain Shams University (ASU), Faculty of Engineering, BSc Graduation Project Students Only (Class 2021)
1. Electronics Engineering (ECE)
1. Electronics Engineering (ECE)
2. Computer Engineering (CSE)
2. Computer Engineering (CSE)
Project Objectives
Project Objectives
The project target is to implement the latest PCIe Physical layer with its features (like: Decoding/Encoding, Byte stripping/un-stripping, Link training, etc.) using Verilog, and verifying the design functionality using Universal Verification Methodology (UVM).
The project target is to implement the latest PCIe Physical layer with its features (like: Decoding/Encoding, Byte stripping/un-stripping, Link training, etc.) using Verilog, and verifying the design functionality using Universal Verification Methodology (UVM).
What Skills Should I have?
What Skills Should I have?
The project needs highly talented and self-motivated students who are highly interested in working in the digital design and verification field.
The project needs highly talented and self-motivated students who are highly interested in working in the digital design and verification field.
Project Supervisors
Project Supervisors
Eng. Haytham Ashour (Engineering Manager at Mentor)
Eng. Haytham Ashour (Engineering Manager at Mentor)
Eng. Mohamed Osama (Engineering Lead at Mentor)
Eng. Mohamed Osama (Engineering Lead at Mentor)
Dr. Hesham Omran
Dr. Hesham Omran
Dr. Mohamed Taher
Dr. Mohamed Taher
Application Deadline
Application Deadline
Your application will be reviewed once we receive it.
Your application will be reviewed once we receive it.
Application deadline is 10-Sep-2020 or until the required number of students is selected.
Application deadline is 10-Sep-2020 or until the required number of students is selected.
We will only contact a shortlisted set of candidates. If you do not receive a reply two weeks after the deadline, then your application was not shortlisted.
We will only contact a shortlisted set of candidates. If you do not receive a reply two weeks after the deadline, then your application was not shortlisted.
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